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<!-- SPDX-License-Identifier: GPL-2.0 -->
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<section id="mds-microarchitectural-data-sampling">
<h1>MDS - Microarchitectural Data Sampling<a class="headerlink" href="#mds-microarchitectural-data-sampling" title="Permalink to this heading">¶</a></h1>
<p>Microarchitectural Data Sampling is a hardware vulnerability which allows
unprivileged speculative access to data which is available in various CPU
internal buffers.</p>
<section id="affected-processors">
<h2>Affected processors<a class="headerlink" href="#affected-processors" title="Permalink to this heading">¶</a></h2>
<p>This vulnerability affects a wide range of Intel processors. The
vulnerability is not present on:</p>
<blockquote>
<div><ul class="simple">
<li><p>Processors from AMD, Centaur and other non Intel vendors</p></li>
<li><p>Older processor models, where the CPU family is < 6</p></li>
<li><p>Some Atoms (Bonnell, Saltwell, Goldmont, GoldmontPlus)</p></li>
<li><p>Intel processors which have the ARCH_CAP_MDS_NO bit set in the
IA32_ARCH_CAPABILITIES MSR.</p></li>
</ul>
</div></blockquote>
<p>Whether a processor is affected or not can be read out from the MDS
vulnerability file in sysfs. See <a class="reference internal" href="#mds-sys-info"><span class="std std-ref">MDS system information</span></a>.</p>
<p>Not all processors are affected by all variants of MDS, but the mitigation
is identical for all of them so the kernel treats them as a single
vulnerability.</p>
</section>
<section id="related-cves">
<h2>Related CVEs<a class="headerlink" href="#related-cves" title="Permalink to this heading">¶</a></h2>
<p>The following CVE entries are related to the MDS vulnerability:</p>
<blockquote>
<div><table class="docutils align-default">
<tbody>
<tr class="row-odd"><td><p>CVE-2018-12126</p></td>
<td><p>MSBDS</p></td>
<td><p>Microarchitectural Store Buffer Data Sampling</p></td>
</tr>
<tr class="row-even"><td><p>CVE-2018-12130</p></td>
<td><p>MFBDS</p></td>
<td><p>Microarchitectural Fill Buffer Data Sampling</p></td>
</tr>
<tr class="row-odd"><td><p>CVE-2018-12127</p></td>
<td><p>MLPDS</p></td>
<td><p>Microarchitectural Load Port Data Sampling</p></td>
</tr>
<tr class="row-even"><td><p>CVE-2019-11091</p></td>
<td><p>MDSUM</p></td>
<td><p>Microarchitectural Data Sampling Uncacheable Memory</p></td>
</tr>
</tbody>
</table>
</div></blockquote>
</section>
<section id="problem">
<h2>Problem<a class="headerlink" href="#problem" title="Permalink to this heading">¶</a></h2>
<p>When performing store, load, L1 refill operations, processors write data
into temporary microarchitectural structures (buffers). The data in the
buffer can be forwarded to load operations as an optimization.</p>
<p>Under certain conditions, usually a fault/assist caused by a load
operation, data unrelated to the load memory address can be speculatively
forwarded from the buffers. Because the load operation causes a fault or
assist and its result will be discarded, the forwarded data will not cause
incorrect program execution or state changes. But a malicious operation
may be able to forward this speculative data to a disclosure gadget which
allows in turn to infer the value via a cache side channel attack.</p>
<p>Because the buffers are potentially shared between Hyper-Threads cross
Hyper-Thread attacks are possible.</p>
<p>Deeper technical information is available in the MDS specific x86
architecture section: <a class="reference internal" href="../../arch/x86/mds.html#mds"><span class="std std-ref">Documentation/arch/x86/mds.rst</span></a>.</p>
</section>
<section id="attack-scenarios">
<h2>Attack scenarios<a class="headerlink" href="#attack-scenarios" title="Permalink to this heading">¶</a></h2>
<p>Attacks against the MDS vulnerabilities can be mounted from malicious non-
privileged user space applications running on hosts or guest. Malicious
guest OSes can obviously mount attacks as well.</p>
<p>Contrary to other speculation based vulnerabilities the MDS vulnerability
does not allow the attacker to control the memory target address. As a
consequence the attacks are purely sampling based, but as demonstrated with
the TLBleed attack samples can be postprocessed successfully.</p>
<section id="web-browsers">
<h3>Web-Browsers<a class="headerlink" href="#web-browsers" title="Permalink to this heading">¶</a></h3>
<blockquote>
<div><p>It’s unclear whether attacks through Web-Browsers are possible at
all. The exploitation through Java-Script is considered very unlikely,
but other widely used web technologies like Webassembly could possibly be
abused.</p>
</div></blockquote>
</section>
</section>
<section id="mds-system-information">
<span id="mds-sys-info"></span><h2>MDS system information<a class="headerlink" href="#mds-system-information" title="Permalink to this heading">¶</a></h2>
<p>The Linux kernel provides a sysfs interface to enumerate the current MDS
status of the system: whether the system is vulnerable, and which
mitigations are active. The relevant sysfs file is:</p>
<p>/sys/devices/system/cpu/vulnerabilities/mds</p>
<p>The possible values in this file are:</p>
<blockquote>
<div><table class="docutils align-default">
<tbody>
<tr class="row-odd"><td><p>‘Not affected’</p></td>
<td><p>The processor is not vulnerable</p></td>
</tr>
<tr class="row-even"><td><p>‘Vulnerable’</p></td>
<td><p>The processor is vulnerable, but no mitigation enabled</p></td>
</tr>
<tr class="row-odd"><td><p>‘Vulnerable: Clear CPU buffers attempted, no microcode’</p></td>
<td><p>The processor is vulnerable but microcode is not updated. The
mitigation is enabled on a best effort basis.</p>
<p>If the processor is vulnerable but the availability of the microcode
based mitigation mechanism is not advertised via CPUID, the kernel
selects a best effort mitigation mode. This mode invokes the mitigation
instructions without a guarantee that they clear the CPU buffers.</p>
<p>This is done to address virtualization scenarios where the host has the
microcode update applied, but the hypervisor is not yet updated to
expose the CPUID to the guest. If the host has updated microcode the
protection takes effect; otherwise a few CPU cycles are wasted
pointlessly.</p>
</td>
</tr>
<tr class="row-even"><td><p>‘Mitigation: Clear CPU buffers’</p></td>
<td><p>The processor is vulnerable and the CPU buffer clearing mitigation is
enabled.</p></td>
</tr>
</tbody>
</table>
</div></blockquote>
<p>If the processor is vulnerable then the following information is appended
to the above information:</p>
<blockquote>
<div><table class="docutils align-default">
<tbody>
<tr class="row-odd"><td><p>‘SMT vulnerable’</p></td>
<td><p>SMT is enabled</p></td>
</tr>
<tr class="row-even"><td><p>‘SMT mitigated’</p></td>
<td><p>SMT is enabled and mitigated</p></td>
</tr>
<tr class="row-odd"><td><p>‘SMT disabled’</p></td>
<td><p>SMT is disabled</p></td>
</tr>
<tr class="row-even"><td><p>‘SMT Host state unknown’</p></td>
<td><p>Kernel runs in a VM, Host SMT state unknown</p></td>
</tr>
</tbody>
</table>
</div></blockquote>
</section>
<section id="mitigation-mechanism">
<h2>Mitigation mechanism<a class="headerlink" href="#mitigation-mechanism" title="Permalink to this heading">¶</a></h2>
<p>The kernel detects the affected CPUs and the presence of the microcode
which is required.</p>
<p>If a CPU is affected and the microcode is available, then the kernel
enables the mitigation by default. The mitigation can be controlled at boot
time via a kernel command line option. See
<a class="reference internal" href="#mds-mitigation-control-command-line"><span class="std std-ref">Mitigation control on the kernel command line</span></a>.</p>
<section id="cpu-buffer-clearing">
<span id="cpu-buffer-clear"></span><h3>CPU buffer clearing<a class="headerlink" href="#cpu-buffer-clearing" title="Permalink to this heading">¶</a></h3>
<blockquote>
<div><p>The mitigation for MDS clears the affected CPU buffers on return to user
space and when entering a guest.</p>
<p>If SMT is enabled it also clears the buffers on idle entry when the CPU
is only affected by MSBDS and not any other MDS variant, because the
other variants cannot be protected against cross Hyper-Thread attacks.</p>
<p>For CPUs which are only affected by MSBDS the user space, guest and idle
transition mitigations are sufficient and SMT is not affected.</p>
</div></blockquote>
</section>
<section id="virtualization-mitigation">
<span id="virt-mechanism"></span><h3>Virtualization mitigation<a class="headerlink" href="#virtualization-mitigation" title="Permalink to this heading">¶</a></h3>
<blockquote>
<div><p>The protection for host to guest transition depends on the L1TF
vulnerability of the CPU:</p>
<ul>
<li><p>CPU is affected by L1TF:</p>
<p>If the L1D flush mitigation is enabled and up to date microcode is
available, the L1D flush mitigation is automatically protecting the
guest transition.</p>
<p>If the L1D flush mitigation is disabled then the MDS mitigation is
invoked explicit when the host MDS mitigation is enabled.</p>
<p>For details on L1TF and virtualization see:
<a class="reference internal" href="l1tf.html#mitigation-control-kvm"><span class="std std-ref">Documentation/admin-guide/hw-vuln//l1tf.rst</span></a>.</p>
</li>
<li><p>CPU is not affected by L1TF:</p>
<p>CPU buffers are flushed before entering the guest when the host MDS
mitigation is enabled.</p>
</li>
</ul>
<p>The resulting MDS protection matrix for the host to guest transition:</p>
<table class="docutils align-default">
<tbody>
<tr class="row-odd"><td><p>L1TF</p></td>
<td><p>MDS</p></td>
<td><p>VMX-L1FLUSH</p></td>
<td><p>Host MDS</p></td>
<td><p>MDS-State</p></td>
</tr>
<tr class="row-even"><td><p>Don’t care</p></td>
<td><p>No</p></td>
<td><p>Don’t care</p></td>
<td><p>N/A</p></td>
<td><p>Not affected</p></td>
</tr>
<tr class="row-odd"><td><p>Yes</p></td>
<td><p>Yes</p></td>
<td><p>Disabled</p></td>
<td><p>Off</p></td>
<td><p>Vulnerable</p></td>
</tr>
<tr class="row-even"><td><p>Yes</p></td>
<td><p>Yes</p></td>
<td><p>Disabled</p></td>
<td><p>Full</p></td>
<td><p>Mitigated</p></td>
</tr>
<tr class="row-odd"><td><p>Yes</p></td>
<td><p>Yes</p></td>
<td><p>Enabled</p></td>
<td><p>Don’t care</p></td>
<td><p>Mitigated</p></td>
</tr>
<tr class="row-even"><td><p>No</p></td>
<td><p>Yes</p></td>
<td><p>N/A</p></td>
<td><p>Off</p></td>
<td><p>Vulnerable</p></td>
</tr>
<tr class="row-odd"><td><p>No</p></td>
<td><p>Yes</p></td>
<td><p>N/A</p></td>
<td><p>Full</p></td>
<td><p>Mitigated</p></td>
</tr>
</tbody>
</table>
<p>This only covers the host to guest transition, i.e. prevents leakage from
host to guest, but does not protect the guest internally. Guests need to
have their own protections.</p>
</div></blockquote>
</section>
<section id="xeon-phi-specific-considerations">
<span id="xeon-phi"></span><h3>XEON PHI specific considerations<a class="headerlink" href="#xeon-phi-specific-considerations" title="Permalink to this heading">¶</a></h3>
<blockquote>
<div><p>The XEON PHI processor family is affected by MSBDS which can be exploited
cross Hyper-Threads when entering idle states. Some XEON PHI variants allow
to use MWAIT in user space (Ring 3) which opens an potential attack vector
for malicious user space. The exposure can be disabled on the kernel
command line with the ‘ring3mwait=disable’ command line option.</p>
<p>XEON PHI is not affected by the other MDS variants and MSBDS is mitigated
before the CPU enters a idle state. As XEON PHI is not affected by L1TF
either disabling SMT is not required for full protection.</p>
</div></blockquote>
</section>
<section id="smt-control">
<span id="mds-smt-control"></span><h3>SMT control<a class="headerlink" href="#smt-control" title="Permalink to this heading">¶</a></h3>
<blockquote>
<div><p>All MDS variants except MSBDS can be attacked cross Hyper-Threads. That
means on CPUs which are affected by MFBDS or MLPDS it is necessary to
disable SMT for full protection. These are most of the affected CPUs; the
exception is XEON PHI, see <a class="reference internal" href="#xeon-phi"><span class="std std-ref">XEON PHI specific considerations</span></a>.</p>
<p>Disabling SMT can have a significant performance impact, but the impact
depends on the type of workloads.</p>
<p>See the relevant chapter in the L1TF mitigation documentation for details:
<a class="reference internal" href="l1tf.html#smt-control"><span class="std std-ref">Documentation/admin-guide/hw-vuln/l1tf.rst</span></a>.</p>
</div></blockquote>
</section>
</section>
<section id="mitigation-control-on-the-kernel-command-line">
<span id="mds-mitigation-control-command-line"></span><h2>Mitigation control on the kernel command line<a class="headerlink" href="#mitigation-control-on-the-kernel-command-line" title="Permalink to this heading">¶</a></h2>
<p>The kernel command line allows to control the MDS mitigations at boot
time with the option “mds=”. The valid arguments for this option are:</p>
<blockquote>
<div><table class="docutils align-default">
<tbody>
<tr class="row-odd"><td><p>full</p></td>
<td><p>If the CPU is vulnerable, enable all available mitigations
for the MDS vulnerability, CPU buffer clearing on exit to
userspace and when entering a VM. Idle transitions are
protected as well if SMT is enabled.</p>
<p>It does not automatically disable SMT.</p>
</td>
</tr>
<tr class="row-even"><td><p>full,nosmt</p></td>
<td><p>The same as mds=full, with SMT disabled on vulnerable
CPUs. This is the complete mitigation.</p></td>
</tr>
<tr class="row-odd"><td><p>off</p></td>
<td><p>Disables MDS mitigations completely.</p></td>
</tr>
</tbody>
</table>
</div></blockquote>
<p>Not specifying this option is equivalent to “mds=full”. For processors
that are affected by both TAA (TSX Asynchronous Abort) and MDS,
specifying just “mds=off” without an accompanying “tsx_async_abort=off”
will have no effect as the same mitigation is used for both
vulnerabilities.</p>
</section>
<section id="mitigation-selection-guide">
<h2>Mitigation selection guide<a class="headerlink" href="#mitigation-selection-guide" title="Permalink to this heading">¶</a></h2>
<section id="trusted-userspace">
<h3>1. Trusted userspace<a class="headerlink" href="#trusted-userspace" title="Permalink to this heading">¶</a></h3>
<blockquote>
<div><p>If all userspace applications are from a trusted source and do not
execute untrusted code which is supplied externally, then the mitigation
can be disabled.</p>
</div></blockquote>
</section>
<section id="virtualization-with-trusted-guests">
<h3>2. Virtualization with trusted guests<a class="headerlink" href="#virtualization-with-trusted-guests" title="Permalink to this heading">¶</a></h3>
<blockquote>
<div><p>The same considerations as above versus trusted user space apply.</p>
</div></blockquote>
</section>
<section id="virtualization-with-untrusted-guests">
<h3>3. Virtualization with untrusted guests<a class="headerlink" href="#virtualization-with-untrusted-guests" title="Permalink to this heading">¶</a></h3>
<blockquote>
<div><p>The protection depends on the state of the L1TF mitigations.
See <a class="reference internal" href="#virt-mechanism"><span class="std std-ref">Virtualization mitigation</span></a>.</p>
<p>If the MDS mitigation is enabled and SMT is disabled, guest to host and
guest to guest attacks are prevented.</p>
</div></blockquote>
</section>
</section>
<section id="default-mitigations">
<span id="mds-default-mitigations"></span><h2>Default mitigations<a class="headerlink" href="#default-mitigations" title="Permalink to this heading">¶</a></h2>
<blockquote>
<div><p>The kernel default mitigations for vulnerable processors are:</p>
<ul class="simple">
<li><p>Enable CPU buffer clearing</p></li>
</ul>
<p>The kernel does not by default enforce the disabling of SMT, which leaves
SMT systems vulnerable when running untrusted code. The same rationale as
for L1TF applies.
See <a class="reference internal" href="l1tf.html#default-mitigations"><span class="std std-ref">Documentation/admin-guide/hw-vuln//l1tf.rst</span></a>.</p>
</div></blockquote>
</section>
</section>
</div>
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